Day 61: HDLBits daily: working through “Circuits” (part 1)
HDLBits: Circuits, part 1
HDLBits is an online judge of small Verilog problems with instant checking — the single most effective RTL interview prep available. Starting today, make it a daily habit and work through the Circuits section: combinational logic, multiplexers, arithmetic, and karnaugh-map problems. Each one is small, but the volume builds the fluency that timed RTL rounds (Qualcomm, NVIDIA, Samsung) demand.
module top_module (
input [3:0] a, b,
input [2:0] op,
output reg [3:0] y
);
always @(*) begin
case (op)
3'd0: y = a & b;
3'd1: y = a | b;
3'd2: y = a ^ b;
3'd3: y = a + b;
3'd4: y = a - b;
default: y = 4'b0; // default -> no latch
endcase
end
endmoduleWhy HDLBits beats reading
You can't fake RTL fluency by reading — you build it by writing hundreds of small correct modules until the patterns (mux, decoder, default-then-case, registered output) are muscle memory. HDLBits' instant feedback turns that into a fast loop. The roadmap says *complete it*; treat it as the daily warm-up for the whole stage.
Progress for Day 61
What is the main reason HDLBits is such effective RTL interview preparation?
