Day 60: Reset strategies: sync vs async assert, sync de-assert
Reset strategies
Every flip-flop needs a defined starting state. Synchronous reset takes effect only on a clock edge (reset is just another input to the logic); asynchronous reset takes effect immediately, independent of the clock. Each has trade-offs: sync reset needs a running clock and adds to the data path; async reset works without a clock but its *release* must be handled carefully to avoid metastability.
// asynchronous assertion, synchronous de-assertion (reset synchronizer)
reg rst_n_sync_1, rst_n_sync_2;
always @(posedge clk or negedge arst_n) begin
if (!arst_n) {rst_n_sync_2, rst_n_sync_1} <= 2'b00; // assert immediately
else {rst_n_sync_2, rst_n_sync_1} <= {rst_n_sync_1, 1'b1}; // release synced
end
wire rst_n = rst_n_sync_2; // use this clean reset everywhere
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= '0;
else q <= d;Async assert, sync de-assert — recite it
The widely-used compromise: assert reset asynchronously (so the chip resets even with no clock) but de-assert it synchronously (so all flip-flops leave reset on the same edge, avoiding a metastable 'reset removal' race). The little reset synchronizer above is a standard block. Pick one reset strategy per clock domain and apply it consistently.
Key terms
- Synchronous reset
- Reset that takes effect only at a clock edge; needs a running clock, adds to the data path.
- Asynchronous reset
- Reset that takes effect immediately, independent of the clock.
- Reset synchronizer
- Logic asserting reset asynchronously but releasing it synchronized to the clock.
- Reset recovery/removal
- Timing checks on the reset de-assertion relative to the clock edge (Stage 5).
Before moving on, you should be able to
Why is "asynchronous assert, synchronous de-assert" a popular reset strategy?
