Day 41: The control unit: decoding to control signals
The control unit
The datapath can do many things; the control unit decides *which* for each instruction. It reads the opcode (and funct3/funct7) and produces the control signals that steer the datapath: RegWrite (commit to rd?), ALUSrc (rs2 vs immediate), ALUOp (which operation), MemRead/MemWrite (load/store?), MemToReg (writeback from ALU or memory?), and Branch/Jump (next-PC selection).
RegWrite ALUSrc MemRead MemWrite MemToReg Branch
add (R) 1 0 0 0 0 0
addi (I) 1 1 0 0 0 0
lw (I) 1 1 1 0 1 0
sw (S) 0 1 0 1 - 0
beq (B) 0 0 0 0 - 1Combinational in single-cycle, FSM later
In the single-cycle CPU the control unit is pure combinational logic (opcode in → signals out). In a pipeline (Day 43) those signals travel *with* the instruction through the stage registers, and hazard control adds a small FSM on top. Either way it's the Stage-0 decoder/FSM skill applied to a real instruction set.
Key terms
- Control unit
- Logic that decodes the instruction into datapath control signals.
- RegWrite
- Control signal enabling a write to the destination register.
- MemToReg
- Selects whether writeback data comes from the ALU or from memory (loads).
- ALUOp
- Encoded hint from main control telling ALU control which operation class to perform.
- Branch / Jump
- Control signals that select a non-sequential next PC.
Before moving on, you should be able to
For a store instruction (sw), what should RegWrite and MemWrite be?
