Day 40: The register file and immediate generation
Register file and immediate generation
The register file holds x0–x31 and, for RV32I, needs two read ports and one write port (2R1W): an instruction reads rs1 and rs2 and writes rd in the same cycle. Reads are combinational; the write commits on the clock edge. x0 is special-cased to always read 0 and ignore writes.
Immediate generation unpacks the constant from the instruction. Because each format scrambles the immediate differently (Day 35), the imm-gen block selects and reassembles the right bits per format, then sign-extends to 32 bits. A mux then chooses whether the ALU's second operand is rs2 (R-type) or the immediate (I/S/B/U/J) — one of those datapath muxes from Stage 0.
The x0 write trap
Forgetting to special-case x0 is a classic first-CPU bug: a nop (addi x0,x0,0) or a deliberately-discarded result must *not* actually change x0. Handle it in the register file (writes to index 0 are dropped) and every idiom that relies on x0-as-zero keeps working.
Key terms
- 2R1W register file
- Two combinational read ports and one clocked write port — the RV32I access pattern.
- Immediate generation
- Logic that selects/reassembles the per-format immediate bits and sign-extends them to 32 bits.
- Sign extension
- Replicating the immediate’s top bit to fill the upper bits, preserving signed value.
- ALUSrc mux
- The mux choosing the ALU’s second operand: register rs2 or the immediate.
Before moving on, you should be able to
Why does the immediate-generation block need to know the instruction format?
