Day 26: Finite state machines: Moore vs Mealy, diagram → table → gates
Formalizing sequential behavior
A finite state machine is the model for any controller: a set of states, transitions between them driven by inputs, and outputs. Two flavours differ in *where the output comes from*. A Moore machine's outputs depend only on the current state. A Mealy machine's outputs depend on the state and the current inputs — often needing fewer states, but its outputs can change mid-cycle (and glitch) as inputs change.
The design flow is always the same: state diagram → state table → state assignment → next-state & output logic → gates (or RTL). Choosing Moore vs Mealy is an engineering trade: Moore is safer (registered, glitch-free outputs) and easier to time; Mealy can be smaller and react one cycle sooner. Real designs mix both, and often register a Mealy output to get the best of each.
This is the shape of every ChipX controller
The UART's bit-timing controller, the SPI mode sequencer, the cache's hit/miss/refill logic, and the pipeline's hazard/stall control (Stages 2–3) are all FSMs you'll design with exactly this diagram→table→logic flow. Getting fluent now means the hard parts later are the *datapath*, not the control.
Key terms
- Finite state machine
- A controller model: states, input-driven transitions, and outputs.
- Moore machine
- Outputs depend only on the current state — registered, glitch-free, easy to time.
- Mealy machine
- Outputs depend on state and inputs — often fewer states, but outputs can change within a cycle.
- State table
- A tabular form of the state diagram listing next state and outputs for each state/input.
- State assignment
- Choosing the bit encoding for states (binary, one-hot, gray), affecting logic size and speed.
Before moving on, you should be able to
What distinguishes a Mealy machine from a Moore machine?
