Day 9: The CMOS inverter and its voltage transfer characteristic (VTC)
From transistors to your first real circuit
You now know what a MOSFET does (Stage −1). CMOS — Complementary MOS — pairs the two flavours: a PMOS that conducts when its gate is *low*, and an NMOS that conducts when its gate is *high*. Wire a PMOS on top (to Vdd) and an NMOS below (to ground), tie both gates to the same input and both drains to the same output, and you have the CMOS inverter: the atom of digital design.
How it works
When the input is low, the NMOS is off and the PMOS is on, so the output is pulled up to Vdd (logic 1). When the input is high, the PMOS is off and the NMOS is on, pulling the output to ground (logic 0). The two networks are complementary — exactly one conducts in steady state — so the output always makes it fully to a rail. This is the pull-up network (PUN) / pull-down network (PDN) structure that every CMOS gate follows.
The voltage transfer characteristic (VTC)
Sweep the input from 0 to Vdd and plot the output: that curve is the VTC. It stays high, then drops almost vertically through a switching threshold `Vm` (where Vin = Vout, both transistors momentarily in saturation), then stays low. The steeper that middle region, the more decisively the gate rejects ambiguous inputs — high gain in the transition is exactly what makes digital logic *digital*.
Idealized CMOS inverter VTC (Vdd = 5 V): flat-high, a sharp transition near Vm ≈ Vdd/2, flat-low.
CMOS's superpower: (almost) no static current
In either steady state, one of the two transistors is fully off, so there is no continuous conducting path from Vdd to ground — and therefore almost no static current. Older families (TTL, NMOS-only logic) burned power through resistive pull-ups even while idle. CMOS burning power mainly *while switching* is the entire reason it won, and the foundation of the power equation you meet on Day 11.
Key terms
- CMOS
- Complementary MOS: pairing PMOS (on when gate low) and NMOS (on when gate high) so exactly one network conducts.
- Pull-up / pull-down network
- The PMOS network to Vdd (PUN) and NMOS network to ground (PDN); complementary in every CMOS gate.
- VTC
- Voltage transfer characteristic — output voltage vs input voltage for a gate.
- Switching threshold Vm
- The input voltage where Vin = Vout; the midpoint of the VTC transition, set by the PMOS/NMOS strength ratio.
- Rail-to-rail
- Output reaching fully to Vdd or ground, not an intermediate voltage — a hallmark of static CMOS.
Before moving on, you should be able to
In a CMOS inverter with input held steady at logic 1, what is the state of the two transistors?
