Day 86: ChipX core: single-cycle RV32I (part 3 — first riscv-test pass)
ChipX core: first riscv-test pass (part 3)
Bring the single-cycle core up in Verilator and run the rv32ui tests. Load each test's instructions into instruction memory, run to its pass/fail convention, and — crucially — compare against your Stage-1 ISS running the same program. When your RTL core and your golden model agree on every register, and rv32ui passes, ChipX is unmistakably a working CPU.
# compile the RTL + C++ testbench with Verilator
verilator --cc core_sc.v --exe tb_core.cpp --trace -Wall
make -C obj_dir -f Vcore_sc.mk Vcore_sc
# run one rv32ui test (loads .hex, runs, checks pass convention)
./obj_dir/Vcore_sc rv32ui/add.hex # -> PASS/FAIL
# regression: run all, compare register dumps to the ISS
make test # runs every rv32ui test through RTL and ISS, diffs resultsThe ISS earns its keep
This is why the ISS was 'not a throwaway' (Stage 1). Diffing the RTL's architectural state against the ISS after each instruction pinpoints exactly *which* instruction first diverges — a far better debug signal than 'the test failed'. This RTL-vs-golden-model comparison is a preview of the Stage-3 scoreboard, running on a smaller scale.
Ship for Day 86
How does comparing the RTL core against the Stage-1 ISS help debugging when a test fails?
