Day 75: The AXI4-Lite slave register interface
The AXI4-Lite slave register interface
So the CPU can configure and read peripherals, each exposes a register interface on a standard bus: AXI4-Lite, a simplified AXI for single, non-bursting register accesses. It has five channels — AW (write address), W (write data), B (write response), AR (read address), R (read data) — each using a VALID/READY handshake: the source asserts VALID, the sink asserts READY, and transfer happens the cycle both are high.
// accept a write when both address and data are present
wire aw_hs = awvalid & awready; // address handshake
wire w_hs = wvalid & wready; // data handshake
always @(posedge clk) begin
awready <= !awready & awvalid & wvalid; // simple one-shot accept
wready <= !wready & awvalid & wvalid;
if (aw_hs && w_hs) begin
case (awaddr[7:2])
6'd0: ctrl_reg <= wdata;
6'd1: reload <= wdata;
// ... map registers ...
endcase
bvalid <= 1'b1; // signal write response
end else if (bvalid && bready) bvalid <= 1'b0;
endVALID/READY is the whole protocol
Master AXI looks intimidating, but AXI-Lite is just five VALID/READY channels. The golden rule: VALID must not wait for READY (a source can assert VALID anytime), but transfer only completes when both are high. Internalize this handshake and you understand the backbone of every modern SoC interconnect — and you'll build a VIP for it in Stage 3.
Key terms
- AXI4-Lite
- A lightweight AXI subset for single register reads/writes; no bursts.
- VALID/READY handshake
- Transfer occurs the cycle both VALID (source) and READY (sink) are asserted.
- AW/W/B/AR/R channels
- Write-address, write-data, write-response, read-address, read-data channels.
- Memory-mapped register
- A peripheral control/status register the CPU accesses at a fixed address.
Ship for Day 75
In an AXI VALID/READY handshake, when does a data transfer actually occur?
