Day 72: Peripheral: I²C master
Peripheral: I²C master
I²C runs a multi-device bus on just two wires — SDA (data) and SCL (clock) — both open-drain with pull-ups, so any device can pull low but none drives high. A transfer is framed by a START (SDA falls while SCL high) and STOP (SDA rises while SCL high); each byte is followed by an ACK/NACK bit from the receiver. Devices are selected by a 7-bit address sent first.
START | ADDR[6:0] + W(0) | ACK | DATA byte | ACK | ... | STOP
| | | | | |
slave pulls SDA low for ACK after each byte it accepts.
Open-drain rule: master RELEASES SDA (lets pull-up raise it) to send 1,
and DRIVES it low to send 0. Same for SCL during clock stretching.Open-drain and clock stretching
Because lines are open-drain, your RTL never *drives high* — it drives low or tri-states (releases). A slave can also stretch the clock by holding SCL low when it needs time; a correct master waits for SCL to actually rise before proceeding. These are the details that make I²C fiddlier than SPI, and exactly what interviewers probe.
Key terms
- I²C
- Two-wire (SDA/SCL) multi-device open-drain bus with addressing and per-byte acknowledgement.
- Open-drain
- Outputs that pull low or release; a pull-up provides the high level, so lines are wired-AND.
- START / STOP
- Bus framing: SDA transition while SCL is high marks the beginning/end of a transaction.
- ACK / NACK
- Receiver’s acknowledge (SDA low) or not-acknowledge (SDA high) after each byte.
- Clock stretching
- A slave holding SCL low to pause the master until it is ready.
Ship for Day 72
Why must an I²C master never actively drive SDA or SCL high?
