Day 55: Ship Stage 1: the golden-model ISS + the annotated paper pipeline
Ship Stage 1: the golden ISS + paper pipeline
Stage 1 ships two load-bearing artifacts. First, the RV32I ISS — passing rv32ui, running compiled C, with a make test — which becomes the golden reference model for Stage 3 verification. Second, the complete paper pipeline design: the single-cycle datapath evolved into the annotated 5-stage pipeline, every forwarding path, stall, and flush drawn and labeled, scanned into docs/stage1/.
Stage 1 exit criteria
- Draw the 5-stage pipeline from memory: registers, muxes, forwarding paths, hazard-unit I/O
- Hand-execute a 10-instruction sequence through the pipeline, showing stalls and forwards cycle by cycle
- ISS passes rv32ui; repo has a CI-style make test
- Answer cold: "Why does a load-use hazard need a stall even with full forwarding?"
You de-risked Stage 2
This is why the roadmap could trim Stage 2 to 40 days: the *hard thinking* — the ISA, the datapath, the hazards — is done, and you have a golden model to check the RTL against. Stage 2 becomes 'translate the paper CPU into synthesizable Verilog,' not 'figure out how a CPU works while also learning Verilog.'
Next (Stage 2) you become dangerous: Verilog semantics, the peripherals (UART/SPI/I²C/GPIO/timer), CDC and FIFOs, and finally the ChipX core itself — single-cycle first, then pipelined — passing rv32ui in Verilator. Every diagram you drew this stage becomes a module you write.
Stage 1 shipping checklist
Why does completing a thorough ISS and paper design in Stage 1 make Stage 2 (RTL) faster and safer?
