Day 52: Advanced-architecture awareness: superscalar, OoO, Tomasulo (story depth)
Advanced-architecture awareness
ChipX is a simple in-order scalar pipeline — deliberately. But architecture rounds at NVIDIA/Apple/Qualcomm probe how modern high-performance cores go faster, at *whiteboard-story* depth. The two big ideas: superscalar (issue more than one instruction per cycle via duplicated units) and out-of-order (OoO) execution (run instructions as their operands become ready, not in program order, to hide latency).
OoO needs bookkeeping: register renaming (map architectural registers to a larger physical set to break false dependencies), Tomasulo's algorithm with reservation stations (hold instructions until operands arrive), a reorder buffer (ROB) (retire results in program order for correct exceptions), and speculation (execute past unresolved branches, squash if wrong). You should be able to *tell the story* of each; implementing them is explicitly ChipX v2.0.
Story depth, not implementation
The scope discipline matters: implementing OoO is a whole project and would blow the frozen spec (failure mode #7). Learn to *narrate* superscalar/OoO/Tomasulo/ROB/renaming convincingly — that's what the interview wants — and keep ChipX in-order. 'I understand OoO and chose in-order for a first tapeout' is a mature, defensible position.
Key terms
- Superscalar
- Issuing multiple instructions per cycle using duplicated execution resources.
- Out-of-order execution
- Executing instructions as operands become ready rather than in program order.
- Register renaming
- Mapping architectural registers to a larger physical set to remove false dependencies.
- Reorder buffer (ROB)
- Structure that retires results in program order so exceptions remain precise.
- Speculation
- Executing past unresolved branches and squashing the work if the guess was wrong.
Before moving on, you should be able to
What is the primary purpose of a reorder buffer (ROB) in an out-of-order CPU?
