Day 43: Pipelining: the five stages and the pipeline registers
Pipelining: the five stages
The single-cycle CPU wastes the datapath: while the ALU works, the instruction memory and register file sit idle. Pipelining overlaps instructions like an assembly line, splitting execution into five stages — IF (fetch), ID (decode/read registers), EX (execute/ALU), MEM (memory access), WB (writeback) — with pipeline registers latching each stage's results for the next. Five instructions are in flight at once, one finishing every (much shorter) cycle.
The payoff is throughput: ideal speedup approaches the number of stages (≈5×), because the clock period is set by the *slowest single stage* rather than the whole instruction. It doesn't reduce any one instruction's latency — that stays five cycles — but it dramatically raises how many complete per second. The catch is hazards (Days 44–47), where overlapping instructions interfere.
Latency vs throughput
A car takes the same time to build whether or not there's an assembly line — but the factory ships far more cars per day. Pipelining is that line: each instruction still takes 5 stages (latency unchanged), yet one *completes* every cycle (throughput up ~5×). Interviewers love this distinction; state it crisply.
Key terms
- Pipelining
- Overlapping instruction execution across stages so one completes per cycle.
- IF/ID/EX/MEM/WB
- The classic five stages: fetch, decode, execute, memory, writeback.
- Pipeline register
- A register between stages latching one instruction’s intermediate results and control.
- Throughput vs latency
- Instructions completed per unit time vs the time for one instruction; pipelining raises the former, not the latter.
- Hazard
- A situation where overlapping instructions would produce a wrong result without extra handling.
Before moving on, you should be able to
Pipelining a single-cycle CPU into five stages primarily improves which metric?
