Day 3: Ship the fab note + yield worksheet
Ship day: the fab-to-package note + yield worksheet
Every stage of this roadmap ends with a committed, demoable artifact — if it can't be shown, the stage isn't done. Today you consolidate Days 1–2 into ChipX's first two deliverables and set up the repository you'll live in for 300 days. Writing the note in your own words is the point: explaining photolithography to an imaginary reader is how you discover which parts you only *thought* you understood.
Set up the repo (Git from Day 1)
Professional workflow starts now, not in Stage 2. Create the chipx/ repository with the layout you'll grow into. Empty directories with a .gitkeep are fine — the structure itself is a commitment to where things live.
chipx/
docs/ # specs, block diagrams, verification plan, reports
stage_minus1/
sand_to_package.md
yield_worksheet.md
devices.md # (grows on Day 8)
rtl/ # core/, periph/, fabric/, top/ (Stage 2)
tb/ # sv/ (UVM env), cocotb/, vectors/ (Stage 3)
fw/ # C firmware, linker scripts (Stage 4)
fpga/ # constraints, board tops, bitstreams (Stage 4)
asic/ # sdc/, yosys/, openlane/, signoff/ (Stage 5-7)
scripts/ # Python + TCL + Make glue
sim/ # simulator makefiles, waves, coverageWhat the fab note must cover
- The photolithography loop, end-to-end, in your own words
- FEOL vs BEOL, and what the metal stack + CMP are for
- Doping: diffusion vs ion implantation, and what n/p regions become
- Packaging: wire bond vs flip-chip, and the OSAT role
- One hand-drawn transistor cross-section through the metal stack (scan/photo it in)
The yield worksheet
Pick a ChipX-class die area, then tabulate gross die per wafer and Poisson yield at two or three defect densities, and note the resulting good-die count. The goal isn't precision — it's building the reflex to reason about cost the way a real design team does.
# ChipX yield worksheet
Wafer: 300 mm · Die: 2 mm x 2 mm · Area A = 0.04 cm^2
Gross die per wafer (est.): ~17,700
| D0 (/cm^2) | Yield = exp(-A*D0) | Good dies | Notes |
|-----------:|-------------------:|----------:|-----------------------|
| 0.1 | 0.996 | ~17,600 | mature node |
| 0.5 | 0.980 | ~17,300 | typical |
| 1.0 | 0.961 | ~17,000 | immature / large die |
Takeaway: at this tiny area, yield barely moves — the cost lever is
DIE AREA, not D0. Now recompute for a 4 cm^2 die and watch yield fall off a cliff.Good dies per 300 mm wafer for the small ChipX die vs a 20× larger die, at D0 = 0.5 /cm².
Ship: docs/stage_minus1/sand_to_package.md + yield_worksheet.md
Write the 2-page fab note in your own words with one hand-drawn cross-section, fill in the yield worksheet for your chosen die area, and commit both. This is ChipX commit #1 — from here, every stage adds an artifact, never a tutorial you merely watched.
Watch one thing, then write
Consolidate with a single high-quality end-to-end explainer (Branch Education's *How are Microchips Made?* or an Asianometry fab video from the named list) — then close the tab and write. The named-resources rule exists because VLSI YouTube is infinite and shallow; tutorial hopping is the #1 killer of VLSI self-study.
Stage −1 shipping checklist (so far)
Your yield worksheet shows a 0.04 cm² die and a 4 cm² die at the same D0. Why does the big die cost so much more per good chip?
