Day 22: Sequential logic I: SR latch → D latch → D flip-flop (from NANDs)
Adding memory to logic
Combinational logic forgets everything the instant inputs change. To *store* a bit you need feedback. Cross-couple two NAND (or NOR) gates and you get an SR latch: Set forces the output to 1, Reset to 0, and with neither asserted it holds its last value. (The both-asserted input is forbidden — it breaks the complementary outputs.) That feedback loop is the seed of all memory.
Latch → flip-flop
A gated D latch adds a data input and an enable: while enable is high it's transparent (output follows D); while low it holds. It's level-sensitive — a risk, because it passes glitches whenever it's open. A D flip-flop fixes this by being edge-triggered: it samples D only at the clock *edge*. The standard build is master-slave — two latches on opposite clock phases, so exactly one is transparent at a time and data advances one stage per edge.
'Never infer a latch' starts here
In Stage 2 the cardinal RTL sin is *accidentally* describing a latch (by leaving a combinational output unassigned on some path). To avoid it, you have to know exactly what a latch is — a level-sensitive, transparent memory — and how it differs from the edge-triggered flip-flop you almost always want. This day is the foundation of that instinct.
Key terms
- SR latch
- Cross-coupled NAND/NOR gates that set, reset, or hold a bit; the both-asserted input is forbidden.
- Gated D latch
- A level-sensitive one-bit store: transparent (Q follows D) while enabled, holds otherwise.
- D flip-flop
- An edge-triggered store that samples D only at the clock edge.
- Master-slave
- Two latches on opposite clock phases forming an edge-triggered flip-flop.
- Transparent / level-sensitive
- A latch state where the output follows the input for the whole time the enable is active.
Ship for Day 22
What is the key behavioral difference between a D latch and a D flip-flop?
