Day 13: Transmission gates + transistor-level NAND/NOR on paper
Building gates from the PUN/PDN pattern
A static CMOS gate is always a pull-down network of NMOS (connecting the output to ground for the input combinations that should output 0) and a complementary pull-up network of PMOS (connecting to Vdd for the rest). Series NMOS implements AND-of-inputs in the PDN; parallel NMOS implements OR. The PUN is the dual. Get this and NAND, NOR, AOI, and every other gate follow mechanically.
NAND vs NOR at the transistor level
A 2-input NAND pulls low only when *both* inputs are high → two NMOS in series (PDN), and two PMOS in parallel (PUN). A 2-input NOR pulls low when *either* input is high → two NMOS in parallel, two PMOS in series. The difference matters because series transistors are slower (higher resistance, and the Stage −1 body effect on the upper device).
Why designers prefer NAND over NOR
PMOS is intrinsically weaker than NMOS (holes have lower mobility, Stage −1). NOR puts the weak PMOS devices in series in the pull-up, making it slow; NAND puts them in parallel. So CMOS libraries and synthesis lean on NAND-heavy structures — a fact worth stating in an interview.
The transmission gate
Put an NMOS and a PMOS in parallel, driven by complementary controls, and you get a transmission gate — a bidirectional analog switch that passes a *full* rail in both directions (the NMOS passes a strong 0, the PMOS a strong 1, together they pass both cleanly). It's the building block of CMOS multiplexers and latches, both of which you'll meet later this stage.
Key terms
- Pull-down network (PDN)
- The NMOS network that connects the output to ground; series = AND, parallel = OR of inputs.
- Pull-up network (PUN)
- The complementary PMOS network to Vdd; the dual of the PDN.
- Series vs parallel stack
- Series transistors implement AND and are slower (added resistance + body effect); parallel implement OR.
- Transmission gate
- Parallel NMOS+PMOS switch passing a full rail both ways; used in muxes and latches.
- AOI / OAI
- And-Or-Invert / Or-And-Invert compound gates — efficient single-stage CMOS structures.
On paper, you should be able to
Why is a CMOS NOR gate generally slower than a CMOS NAND gate of the same size?
