Day 11: Dynamic vs static vs leakage power; the P = αCV²f equation
The power equation
A CMOS chip's power splits cleanly: P_total = P_dynamic + P_short-circuit + P_static. The headline term is dynamic (switching) power, P_dynamic = α · C · V² · f. Every symbol is something you can now reason about — and every one is a lever a real design team pulls.
P_dynamic = alpha * C * V^2 * f
alpha (activity factor) : fraction of nodes that switch per clock (0..1)
C (capacitance) : total switched load capacitance
V (supply voltage) : Vdd
f (frequency) : clock rate
Energy per full 0->1->0 cycle of a node = C * V^2
(half is stored on the cap, half dissipated in the transistor each edge)Where does C·V² come from? Charging a capacitor C to voltage V through the PMOS dissipates ½CV² in the transistor and stores ½CV² on the cap; discharging through the NMOS dissipates the stored half. So one full switching cycle costs CV², times how often it happens (f), times how many nodes actually toggle (α).
Dynamic power vs supply voltage (fixed α, C, f): the V² term means small voltage cuts pay off hugely.
Why voltage is the power lever
Power scales with V² but only *linearly* with f. Halving the voltage quarters dynamic power; halving the frequency only halves it. That asymmetry is the entire basis of DVFS (dynamic voltage & frequency scaling) in Stage 5 — and why lowering voltage, not just slowing the clock, is how chips save the most energy.
The other terms: short-circuit power is that brief both-on current per transition (kept small by fast edges). Static power is the Stage −1 leakage — negligible on old nodes, but a first-class problem on modern ones, which is why P_static earns its own place in the equation and its own Stage 5 toolbox (multi-Vt, power gating).
Key terms
- Activity factor α
- The average fraction of nodes toggling per clock cycle; clock nets have α≈1, random logic much less.
- Dynamic (switching) power
- α·C·V²·f — power spent charging/discharging load capacitance as nodes switch.
- Short-circuit power
- Power from the momentary both-transistors-on current during input transitions.
- Static (leakage) power
- Power burned by leakage while idle; dominated by subthreshold conduction (Stage −1).
- DVFS
- Dynamic voltage & frequency scaling — trading speed for large power savings via the V² term (Stage 5).
Before moving on, you should be able to
A design drops its supply voltage from 1.0 V to 0.7 V (holding α, C, f fixed). Roughly what happens to dynamic power?
