Day 106: The pre-UVM testbench: generator → driver → monitor → scoreboard
The pre-UVM testbench architecture
Assemble the pieces into a class-based environment for the UART — deliberately *before* UVM. The canonical structure: a generator creates transactions, a driver applies them to the DUT via the virtual interface, a monitor observes the DUT's pins and reconstructs transactions, and a scoreboard compares observed behavior against a reference. Mailboxes connect them; a top module instantiates the DUT and interface.
Why build it before UVM
UVM *is* this architecture, standardized and made reusable. Building the raw version by hand — and feeling the boilerplate, the manual connections, the lack of reuse — is exactly why the roadmap has you do it first. When UVM's agent, sequencer, and analysis_port appear (Day 116+), you'll recognize each as 'the standardized version of the thing I hand-wrote'.
Key terms
- Generator
- Creates (randomized) transactions and sends them to the driver.
- Driver
- Applies transactions to the DUT pins via the virtual interface.
- Monitor
- Observes DUT pins and reconstructs transactions for checking/coverage.
- Scoreboard
- Compares observed DUT behavior against an independent reference model.
Before moving on, you should be able to
In the classic testbench architecture, what is the monitor’s job?
