Day 104: SVA I: immediate assertions and the basics
SVA I: immediate assertions
SystemVerilog Assertions (SVA) embed correctness rules directly into simulation (and formal, Stage 5). An immediate assertion is a procedural check evaluated like an if: assert(condition) else $error(...). Use them for simple, single-point invariants — 'a one-hot signal really is one-hot', 'this FIFO never overflows'. They fire the instant the condition is false, pointing straight at the bug.
always @(posedge clk) begin
// FIFO must never overflow
assert (!(full && wr_en)) else $error("FIFO overflow at %0t", $time);
// grant must be one-hot (at most one bit set)
assert ($onehot0(grant)) else $error("grant not one-hot: %b", grant);
endAssertions localize bugs in time
A scoreboard tells you the *final* result was wrong; an assertion tells you the *exact cycle and place* a rule broke. That temporal precision makes debugging dramatically faster. Sprinkle immediate assertions on every internal invariant you can state — they're cheap insurance that turns 'something's wrong somewhere' into 'this line, this cycle'.
Key terms
- SVA
- SystemVerilog Assertions — a language for embedding correctness checks in simulation and formal.
- Immediate assertion
- A procedural, single-point check evaluated like an if; fires when false.
- $onehot / $onehot0
- Built-ins asserting exactly one (or at most one) bit is set.
- Invariant
- A property that must always hold (no overflow, one-hot grant, PC never X).
Before moving on, you should be able to
Compared to a scoreboard, what advantage does an assertion give when a bug occurs?
